Testability Concepts for Digital ICs: The Macro Test Approach by F.P.M. Beenker

Description: Testability Concepts for Digital ICs by F.P.M. Beenker, R.G. Bennetts, A.P. Thijssen Preface Testing Integrated Circuits for manufacturing defects includes four basic disciplines. Thirdly, knowledge of how to create a test program for an IC which is targeted on detecting these defects, and finally, understanding of the hardware, Automatic Test Equipment, to run the test on. FORMAT Hardcover LANGUAGE English CONDITION Brand New Publisher Description This volume considers testability aspects for digital ICs. The strategy taken is to integrate the testability aspects into the design and manufacturing of ICs and, for each IC design project, to give a precise definition of the boundary conditions, responsibilities, interfaces and communications between persons, and quality targets. Macro Test, a design-for-testability approach, provides a manageable test-programme route. Using the Macro Test approach, one can explore alternative solutions to satisfy pre-defined levels of performance (such as defect detection, defect location, test application) within a pre-defined cost budget and time scale. This book presents a tried and proven method of using a Macro approach to testing complex ICs and is intended for all test engineers, IC designers and managers concerned with producing high quality ICs. Table of Contents 1 Introduction.- 1.1 The Main Topic.- 1.2 Test Objectives.- 1.3 Definition of Testability.- 1.4 Problem Statement: Strategies and Requirements.- 1.5 Outline.- 2 Defect-Oriented Testing.- 2.1 Reason.- 2.2 Defects and Faults.- 2.3 Defect-Fault Relationship: Inductive Fault Analysis.- 2.4 Fault-Defect Relationship: Process Monitoring Testing.- 3 Macro Test: A Framework for Testable IC Design.- 3.1 Introduction to the Macro Test Philosophy.- 3.2 Testability Synthesis within the Macro Test Concept.- 3.3 Integration of Macro Test into a Design & Test flow.- 3.4 Summary of Essential Macro Test Items.- 4 Examples of Leaf-Macro Test Techniques.- 4.1 Defect Modeling and Test Algorithm Development for Static Random Access Memories (SRAMs).- 4.2 Built-in Self-Test for Static Random Access Memories.- 4.3 Leaf-Macro Testability Study Aspects.- 5 Scan Chain Routing with Minimal Test Application Time.- 5.1 Leaf-Macro Access.- 5.2 Introduction to Scan Chain Routing.- 5.3 Scan Test Application Protocol.- 5.4 Scan Chain Routing Problem Formulation.- 5.5 Scan Chain Routing Cost Model.- 5.6 Scan Chain Routing Problem Complexity.- 5.7 Routing of Scan Registers into a Single Scan Chain.- 6 Test Control Block Concepts.- 6.1 Introduction.- 6.2 Test Control Block Requirements.- 6.3 Test Controller Architectures.- 6.4 Relation between a Test Control Block and Test Plans.- 6.5 Test Control Block Design Requirements.- 6.6 Optimal Test Control Block implementation.- 6.7 Test Control Block Design Example.- 6.8 Distributed Test Control.- 7 Exploiting Parallelism in Leaf-Macro Access.- 7.1 Introduction.- 7.2 Levels of Parallelism.- 7.3 Formal Definitions of Resources, Resource Compatibility and Parallelism.- 7.4 Test Compatibility Graphs.- 7.5 Resource Allocation versus Test Assembly.- 7.6 AlgorithmicImplementation and Experimental Results.- 8 Timing Aspects of CMOS VLSI Circuits.- 8.1 Introduction.- 8.2 Timing Models of Latches and Flip-Flops.- 8.3 Timing of Data Transfers.- 8.4 Clock Drivers.- List of Symbols and Abbreviations.- References. Promotional Springer Book Archives Long Description Preface Testing Integrated Circuits for manufacturing defects includes four basic disciplines. First of all an understanding of the origin and behaviour of defects. Secondly, knowledge of IC design and IC design styles. Thirdly, knowledge of how to create a test program for an IC which is targeted on detecting these defects, and finally, understanding of the hardware, Automatic Test Equipment, to run the test on. All four items have to be treated, managed, and to a great extent integrated before the term IC quality gets a certain meaning and a test a certain measurable value. The contents of this book reflects our activities on testability concepts for complex digital ICs as performed at Philips Research Laboratories in Eindhoven, The Netherlands. Based on the statements above, we have worked along a long Details ISBN0792396588 Author A.P. Thijssen Short Title TESTABILITY CONCEPTS FOR DIGIT Series Frontiers in Electronic Testing Language English ISBN-10 0792396588 ISBN-13 9780792396581 Media Book Format Hardcover Series Number 3 Year 1995 Publication Date 1995-11-30 Subtitle The Macro Test Approach Place of Publication Dordrecht Publisher Springer Pages 212 Imprint Springer Country of Publication Netherlands DOI 10.1007/b117403;10.1007/978-1-4615-2365-9 Edition Description 1995 ed. Edition 1995th Alternative 9781461360049 DEWEY 620.0044 Illustrations IX, 212 p. Audience Professional & Vocational We've got this At The Nile, if you're looking for it, we've got it. With fast shipping, low prices, friendly service and well over a million items - you're bound to find what you want, at a price you'll love! TheNile_Item_ID:96245934;

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